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Once a new service worker has installed and a previous version isn't being used, the new one activates, and you get an activate event.

Because the old version is out of the way, it's a good time to delete unused caches. During activation, other events such as fetch are put into a queue, so a long activation could potentially block page loads.

Keep your activation as lean as possible, only using it for things you couldn't do while the old version was active. An origin can have multiple named Cache objects.

To create a cache or open a connection to an existing cache we use the caches. This returns a promise that resolves to the cache object.

The Cache API comes with several methods that let us create and manipulate data in the cache. These can be grouped into methods that either create, match, or delete data.

There are three methods we can use to add data to the cache. These are add , addAll , and put. In practice, we will call these methods on the cache object returned from caches.

For example:. We call the add method on this object to add the file to that cache. The key for that object will be the request, so we can retrieve this response object again later by this request.

If any of the files fail to be added to the cache, the whole operation will fail and none of the files will be added.

This lets you manually insert the response object. Often, you will just want to fetch one or more requests and then add the result straight to your cache.

In such cases you are better off just using cache. There are a couple of methods to search for specific content in the cache: match and matchAll.

These can be called on the caches object to search through all of the existing caches, or on a specific cache returned from caches.

It returns undefined if no match is found. The first parameter is the request, and the second is an optional list of options to refine the search.

Here are the options as defined by MDN:. For example, if your app has cached some images contained in an image folder, we could return all images and perform some operation on them like this:.

We can delete items in the cache with cache. This method finds the item in the cache matching the request, deletes it, and returns a Promise that resolves to true.

If it doesn't find the item, it resolves to false. It also has the same optional options parameter available to it as the match method.

Finally, we can get a list of cache keys using cache. This returns a Promise that resolves to an array of cache keys.

These will be returned in the same order they were inserted into the cache. Both parameters are optional.

If nothing is passed, cache. If a request is passed, it returns all of the matching requests from the cache. The options are the same as those in the previous methods.

The keys method can also be called on the caches entry point to return the keys for the caches themselves.

This lets you purge outdated caches in one go. Except as otherwise noted, the content of this page is licensed under the Creative Commons Attribution 4.

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Cache read misses from a data cache usually cause a smaller delay, because instructions not dependent on the cache read can be issued and continue execution until the data is returned from main memory, and the dependent instructions can resume execution.

Cache write misses to a data cache generally cause the shortest delay, because the write can be queued and there are few limitations on the execution of subsequent instructions; the processor can continue until the queue is full.

For a detailed introduction to the types of misses, see cache performance measurement and metric. Most general purpose CPUs implement some form of virtual memory.

To summarize, either each program running on the machine sees its own simplified address space , which contains code and data for that program only, or all programs run in a common virtual address space.

A program executes by calculating, comparing, reading and writing to addresses of its virtual address space, rather than addresses of physical address space, making programs simpler and thus easier to write.

Virtual memory requires the processor to translate virtual addresses generated by the program into physical addresses in main memory.

The portion of the processor that does this translation is known as the memory management unit MMU. The fast path through the MMU can perform those translations stored in the translation lookaside buffer TLB , which is a cache of mappings from the operating system's page table , segment table, or both.

For the purposes of the present discussion, there are three important features of address translation:. Some early virtual memory systems were very slow because they required an access to the page table held in main memory before every programmed access to main memory.

The first hardware cache used in a computer system was not actually a data or instruction cache, but rather a TLB.

Caches can be divided into four types, based on whether the index or tag correspond to physical or virtual addresses:. The speed of this recurrence the load latency is crucial to CPU performance, and so most modern level-1 caches are virtually indexed, which at least allows the MMU's TLB lookup to proceed in parallel with fetching the data from the cache RAM.

But virtual indexing is not the best choice for all cache levels. The cost of dealing with virtual aliases grows with cache size, and as a result most level-2 and larger caches are physically indexed.

Caches have historically used both virtual and physical addresses for the cache tags, although virtual tagging is now uncommon.

If the TLB lookup can finish before the cache RAM lookup, then the physical address is available in time for tag compare, and there is no need for virtual tagging.

Large caches, then, tend to be physically tagged, and only small, very low latency caches are virtually tagged. In recent general-purpose CPUs, virtual tagging has been superseded by vhints, as described below.

A cache that relies on virtual indexing and tagging becomes inconsistent after the same virtual address is mapped into different physical addresses homonym , which can be solved by using physical address for tagging, or by storing the address space identifier in the cache line.

However, the latter approach does not help against the synonym problem, in which several cache lines end up storing data for the same physical address.

Writing to such locations may update only one location in the cache, leaving the others with inconsistent data. This issue may be solved by using non-overlapping memory layouts for different address spaces, or otherwise the cache or a part of it must be flushed when the mapping changes.

The great advantage of virtual tags is that, for associative caches, they allow the tag match to proceed before the virtual to physical translation is done.

However, coherence probes and evictions present a physical address for action. The hardware must have some means of converting the physical addresses into a cache index, generally by storing physical tags as well as virtual tags.

For comparison, a physically tagged cache does not need to keep virtual tags, which is simpler. When a virtual to physical mapping is deleted from the TLB, cache entries with those virtual addresses will have to be flushed somehow.

Alternatively, if cache entries are allowed on pages not mapped by the TLB, then those entries will have to be flushed when the access rights on those pages are changed in the page table.

It is also possible for the operating system to ensure that no virtual aliases are simultaneously resident in the cache.

The operating system makes this guarantee by enforcing page coloring, which is described below. It has not been used recently, as the hardware cost of detecting and evicting virtual aliases has fallen and the software complexity and performance penalty of perfect page coloring has risen.

It can be useful to distinguish the two functions of tags in an associative cache: they are used to determine which way of the entry set to select, and they are used to determine if the cache hit or missed.

The second function must always be correct, but it is permissible for the first function to guess, and get the wrong answer occasionally.

Some processors e. The virtual tags are used for way selection, and the physical tags are used for determining hit or miss.

This kind of cache enjoys the latency advantage of a virtually tagged cache, and the simple software interface of a physically tagged cache. It bears the added cost of duplicated tags, however.

Also, during miss processing, the alternate ways of the cache line indexed have to be probed for virtual aliases and any matches evicted. The extra area and some latency can be mitigated by keeping virtual hints with each cache entry instead of virtual tags.

These hints are a subset or hash of the virtual tag, and are used for selecting the way of the cache from which to get data and a physical tag.

Like a virtually tagged cache, there may be a virtual hint match but physical tag mismatch, in which case the cache entry with the matching hint must be evicted so that cache accesses after the cache fill at this address will have just one hint match.

Since virtual hints have fewer bits than virtual tags distinguishing them from one another, a virtually hinted cache suffers more conflict misses than a virtually tagged cache.

In these processors the virtual hint is effectively two bits, and the cache is four-way set associative. Effectively, the hardware maintains a simple permutation from virtual address to cache index, so that no content-addressable memory CAM is necessary to select the right one of the four ways fetched.

Large physically indexed caches usually secondary caches run into a problem: the operating system rather than the application controls which pages collide with one another in the cache.

Differences in page allocation from one program run to the next lead to differences in the cache collision patterns, which can lead to very large differences in program performance.

These differences can make it very difficult to get a consistent and repeatable timing for a benchmark run.

Sequential physical pages map to sequential locations in the cache until after pages the pattern wraps around.

We can label each physical page with a color of 0— to denote where in the cache it can go. Locations within physical pages with different colors cannot conflict in the cache.

But they should also ensure that the access patterns do not have conflict misses. One way to think about this problem is to divide up the virtual pages the program uses and assign them virtual colors in the same way as physical colors were assigned to physical pages before.

Programmers can then arrange the access patterns of their code so that no two pages with the same virtual color are in use at the same time. There is a wide literature on such optimizations e.

The snag is that while all the pages in use at any given moment may have different virtual colors, some may have the same physical colors.

In fact, if the operating system assigns physical pages to virtual pages randomly and uniformly, it is extremely likely that some pages will have the same physical color, and then locations from those pages will collide in the cache this is the birthday paradox.

The solution is to have the operating system attempt to assign different physical color pages to different virtual colors, a technique called page coloring.

Although the actual mapping from virtual to physical color is irrelevant to system performance, odd mappings are difficult to keep track of and have little benefit, so most approaches to page coloring simply try to keep physical and virtual page colors the same.

If the operating system can guarantee that each physical page maps to only one virtual color, then there are no virtual aliases, and the processor can use virtually indexed caches with no need for extra virtual alias probes during miss handling.

Alternatively, the OS can flush a page from the cache whenever it changes from one virtual color to another. Modern processors have multiple interacting on-chip caches.

The operation of a particular cache can be completely specified by the cache size, the cache block size, the number of blocks in a set, the cache set replacement policy, and the cache write policy write-through or write-back.

While all of the cache blocks in a particular cache are the same size and have the same associativity, typically the "lower-level" caches called Level 1 cache have a smaller number of blocks, smaller block size, and fewer blocks in a set, but have very short access times.

Level 2 and above have progressively larger numbers of blocks, larger block size, more blocks in a set, and relatively longer access times, but are still much faster than main memory.

Cache entry replacement policy is determined by a cache algorithm selected to be implemented by the processor designers.

In some cases, multiple algorithms are provided for different kinds of work loads. Pipelined CPUs access memory from multiple points in the pipeline : instruction fetch, virtual-to-physical address translation, and data fetch see classic RISC pipeline.

The natural design is to use different physical caches for each of these points, so that no one physical resource has to be scheduled to service two points in the pipeline.

Thus the pipeline naturally ends up with at least three separate caches instruction, TLB , and data , each specialized to its particular role.

A victim cache is a cache used to hold blocks evicted from a CPU cache upon replacement. The victim cache lies between the main cache and its refill path, and holds only those blocks of data that were evicted from the main cache.

The victim cache is usually fully associative, and is intended to reduce the number of conflict misses. Many commonly used programs do not require an associative mapping for all the accesses.

In fact, only a small fraction of the memory accesses of the program require high associativity. The victim cache exploits this property by providing high associativity to only these accesses.

A trace cache stores instructions either after they have been decoded, or as they are retired. Generally, instructions are added to trace caches in groups representing either individual basic blocks or dynamic instruction traces.

Having this, the next time an instruction is needed, it does not have to be decoded into micro-ops again.

The WCC's task is reducing number of writes to the L2 cache. Fetching complete pre-decoded instructions eliminates the need to repeatedly decode variable length complex instructions into simpler fixed-length micro-operations, and simplifies the process of predicting, fetching, rotating and aligning fetched instructions.

The main disadvantage of the trace cache, leading to its power inefficiency, is the hardware complexity required for its heuristic deciding on caching and reusing dynamically created instruction traces.

A branch target cache or branch target instruction cache , the name used on ARM microprocessors, [38] is a specialized cache which holds the first few instructions at the destination of a taken branch.

This is used by low-powered processors which do not need a normal instruction cache because the memory system is capable of delivering instructions fast enough to satisfy the CPU without one.

However, this only applies to consecutive instructions in sequence; it still takes several cycles of latency to restart instruction fetch at a new address, causing a few cycles of pipeline bubble after a control transfer.

A branch target cache provides instructions for those few cycles avoiding a delay after most taken branches. This allows full-speed operation with a much smaller cache than a traditional full-time instruction cache.

Smart cache is a level 2 or level 3 caching method for multiple execution cores, developed by Intel. Smart Cache shares the actual cache memory between the cores of a multi-core processor.

In comparison to a dedicated per-core cache, the overall cache miss rate decreases when not all cores need equal parts of the cache space. Consequently, a single core can use the full level 2 or level 3 cache, if the other cores are inactive.

Another issue is the fundamental tradeoff between cache latency and hit rate. Larger caches have better hit rates but longer latency.

To address this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger, slower caches.

Multi-level caches generally operate by checking the fastest, level 1 L1 cache first; if it hits, the processor proceeds at high speed.

If that smaller cache misses, the next fastest cache level 2 , L2 is checked, and so on, before accessing external memory. As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on-chip cache.

Price-sensitive designs used this to pull the entire cache hierarchy on-chip, but by the s some of the highest-performance designs returned to having large off-chip caches, which is often implemented in eDRAM and mounted on a multi-chip module , as a fourth cache level.

The benefits of L3 and L4 caches depend on the application's access patterns. Examples of products incorporating L3 and L4 caches include the following:.

Finally, at the other end of the memory hierarchy, the CPU register file itself can be considered the smallest, fastest cache in the system, with the special characteristic that it is scheduled in software—typically by a compiler, as it allocates registers to hold values retrieved from main memory for, as an example, loop nest optimization.

However, with register renaming most compiler register assignments are reallocated dynamically by hardware at runtime into a register bank, allowing the CPU to break false data dependencies and thus easing pipeline hazards.

Register files sometimes also have hierarchy: The Cray-1 circa had eight address "A" and eight scalar data "S" registers that were generally usable.

There was also a set of 64 address "B" and 64 scalar data "T" registers that took longer to access, but were faster than main memory.

The "B" and "T" registers were provided because the Cray-1 did not have a data cache. The Cray-1 did, however, have an instruction cache. When considering a chip with multiple cores , there is a question of whether the caches should be shared or local to each core.

Implementing shared cache inevitably introduces more wiring and complexity. But then, having one cache per chip , rather than core , greatly reduces the amount of space needed, and thus one can include a larger cache.

Typically, sharing the L1 cache is undesirable because the resulting increase in latency would make each core run considerably slower than a single-core chip.

However, for the highest-level cache, the last one called before accessing memory, having a global cache is desirable for several reasons, such as allowing a single core to use the whole cache, reducing data redundancy by making it possible for different processes or threads to share cached data, and reducing the complexity of utilized cache coherency protocols.

Shared highest-level cache, which is called before accessing memory, is usually referred to as the last level cache LLC. Additional techniques are used for increasing the level of parallelism when LLC is shared between multiple cores, including slicing it into multiple pieces which are addressing certain ranges of memory addresses, and can be accessed independently.

In a separate cache structure, instructions and data are cached separately, meaning that a cache line is used to cache either instructions or data, but not both; various benefits have been demonstrated with separate data and instruction translation lookaside buffers.

Multi-level caches introduce new design decisions. For instance, in some processors, all data in the L1 cache must also be somewhere in the L2 cache.

These caches are called strictly inclusive. Other processors like the AMD Athlon have exclusive caches: data is guaranteed to be in at most one of the L1 and L2 caches, never in both.

There is no universally accepted name for this intermediate policy; [45] [46] two common names are "non-exclusive" and "partially-inclusive".

The advantage of exclusive caches is that they store more data. This advantage is larger when the exclusive L1 cache is comparable to the L2 cache, and diminishes if the L2 cache is many times larger than the L1 cache.

When the L1 misses and the L2 hits on an access, the hitting cache line in the L2 is exchanged with a line in the L1.

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